Integrated devices, and especially memories, are usually synchronized by a master clock signal. However, very often these integrated devices also require signals that are phase-shifted with respect to each other by a value less than a period of the clock signal; for example, these signals are used during data latching operations, bit line pre-charge operations for reading stored data, and the like.
Usually, the signals are phase-shifted directly within each integrated device (in technical jargon, on-chip); for this purpose, the integrated device is provided with one or more delay lines, each one applying a corresponding delay to an input signal (synchronous with the clock signal), so as to obtain a signal being delayed by this delay. Furthermore, to increase the flexibility of the integrated device, the delay lines are generally programmable, so that a target value of the delay may be set at will.
The delay lines are affected, however, by errors due to a number of reasons—such as an intrinsic variability of a manufacturing process of the integrated device, a change of the operating temperature of the integrated device, a drift of the characteristics of the integrated device, noise afflicting the integrated device, and the like. Said errors may cause substantial variations in the actual value of the delay being applied by each delay line with respect to a nominal value thereof (and hence in the corresponding delayed signals being emitted by it); for example, the actual value of the total delay may be up to 5 times larger than its nominal value.
It is, therefore, clear the need for trimming techniques of the delay lines to improve the accuracy of the delay applied by them; for example, the trimming of a delay line based on the discharge of a capacitor (previously loaded at a predefined voltage) may be obtained by appropriately varying the current used to discharge the capacitor.
A simple known trimming technique is of the open loop type; in this case, a trimming procedure is preliminary performed (e.g., in factory) by measuring the actual value of the delay (set to its target value) and trimming the delay line so that it equals its nominal value.
This technique, however, allows a correction of the static component only of the errors of the delay line (e.g., caused by the variability of the manufacturing process), but it may be completely ineffective with respect to a dynamic component thereof (e.g., caused by the temperature change and the characteristics drift).
A more complex known technique is, instead, of the closed loop type being based on a delay-locked loop (or DLL). In this case, there is used a feedback system comprising a phase detector that continuously measures a phase difference between the clock signal and a control signal, which is derived from the delayed signal (with the target value of the delay) in such a way to have a delay equal to an integer number of periods of the clock signal. The phase detector then trims the delay line according to a phase difference between the clock signal and the control signal, to obtain a locking condition in which these signals are in phase with each other (and thus the delayed signal actually has the target value of the delay).
This technique, however, is particularly expensive in terms of energy consumption, since the DLL should be kept always active because of the time required for reaching the locking condition (without which the delay line cannot be used). This disadvantage is particularly acute in integrated devices that require low power consumption (for example, in portable applications).
In addition, in some applications (e.g., non-volatile memories), the delay to be generated on-chip does not need to be extremely accurate (e.g., 500 ps accuracy over a delay of tens of nanoseconds may be sufficiently accurate); therefore, in such an application, a closed-loop solution may be too costly, while an open loop solution may not be accurate enough.